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M41T62, M41T63 M41T64, M41T65
Serial real-time clocks with alarm
Features
Serial RTC with alarm functions - 400 kHz I2C serial interface - Memory mapped registers for seconds, minutes, hours, day, date, month, year, and century - Tenths/hundredths of seconds register 350 nA timekeeping current at 3 V Timekeeping down to 1.0 V 1.3 V to 4.4 V I2C bus operating voltage - 4.4 V max VCC suitable for lithium-ion battery operation Low operating current of 35 A (at 400 kHz) 32 KHz square wave output is on at power-up. Suitable for driving a microcontroller in lowpower mode. Can be disabled. (M41T62/63/64) Programmable 1 Hz to 32 KHz square wave output (M41T62/63/64) Programmable alarm with interrupt function (M41T62/65) 32 KHz crystal oscillator integrates crystal load capacitors, works with high series resistance crystals

3mm 3mm

QFN16 (Q) 3 mm x 3 mm

Accurate programmable watchdog - 62.5 ms to 31 min timeout Software clock calibration. Can adjust timekeeping to within 2 parts per million (5 seconds per month) Automatic leap year compensation -40 to +85 C operation Very small 3 mm x 3 mm, Lead-free 16-lead QFN

Oscillator stop detection monitors clock operation Table 1. Device summary
Basic RTC M41T62 M41T63 M41T64 M41T65 Alarms OSC fail detect Watchdog Calibration timer SQW output IRQ output WDO output F32K output
May 2010
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www.st.com 1
Contents
M41T62/63/64/65
Contents
1 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.1 2-wire bus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.1.1 2.1.2 2.1.3 2.1.4 2.1.5 Bus not busy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Start data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Stop data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Data valid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.2 2.3
READ mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 WRITE mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3
Clock operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 RTC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Calibrating the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Setting alarm clock registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Watchdog output (WDO - M41T63/65 only) . . . . . . . . . . . . . . . . . . . . . . . 27 Square wave output (M41T62/63/64) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Full-time 32 KHz square wave output (M41T64) . . . . . . . . . . . . . . . . . . . 28 Century bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Output driver pin (M41T62/65) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Oscillator stop detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Initial power-on defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4 5 6 7
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Package mechanical information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
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Contents
8
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
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List of tables
M41T62/63/64/65
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 M41T62 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 M41T63 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 M41T64 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 M41T65 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Alarm repeat modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Square wave output frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Initial power-on default values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Century bits examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Crystal electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Crystals suitable for use with M41T6x series RTCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 QFN16 - 16-lead, quad, flat package, no lead, 3 x 3 mm body size, mechanical data . . . 37 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
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List of figures
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. M41T62 logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 M41T63 logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 M41T64 logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 M41T65 logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 M41T62 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 M41T63 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 M41T64 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 M41T65 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 M41T62 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 M41T63 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 M41T64 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 M41T65 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Hardware hookup for SuperCapTM backup operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Serial bus data transfer sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Acknowledgement sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Slave address location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 READ mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Alternative READ mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 WRITE mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Buffer/transfer registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Crystal accuracy across temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Calibration waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Alarm interrupt reset waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Crystal isolation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Bus timing requirements sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 QFN16 - 16-lead, quad, flat package, no lead, 3 x 3 mm body size, outline . . . . . . . . . . . 37 QFN16 - 16-lead, quad, flat package, no lead, 3 x 3 mm, recommended footprint . . . . . . 38
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Description
M41T62/63/64/65
1
Description
The M41T6x serial access TIMEKEEPER(R) is a low power serial RTC with a built-in 32.768 kHz oscillator. Eight registers are used for the clock/calendar function and are configured in binary coded decimal (BCD) format. An additional 8 registers provide status/control of alarm, 32 KHz output, calibration, and watchdog functions. Addresses and data are transferred serially via a two line, bi-directional I2C interface. The built-in address register is incremented automatically after each WRITE or READ data byte. Functions available to the user include a time-of-day clock/calendar, alarm interrupts (M41T62/65), 32 KHz output (M41T62/63/64), programmable square wave output (M41T62/63/64), and watchdog output (M41T63/65). The eight clock address locations contain the century, year, month, date, day, hour, minute, second and tenths/hundredths of a second in 24 hour BCD format. Corrections for 28-, 29- (leap year), 30- and 31-day months are made automatically. The M41T6x is supplied in a tiny, 3 mm x 3 mm 16-pin QFN which requires a user-supplied 32 KHz crystal. Figure 1. M41T62 logic diagram
VCC
XI XO M41T62 SCL SDA SQW
(2)
IRQ/OUT(1)
VSS
AI09103
1. Open drain. 2. Defaults to 32 KHz on power-up.
Figure 2.
M41T63 logic diagram
VCC
XI XO M41T63 SCL SDA WDO
(1)
SQW(2)
VSS
AI09189
1. Open drain. 2. Defaults to 32 KHz on power-up.
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M41T62/63/64/65 Figure 3. M41T64 logic diagram
VCC
Description
XI XO M41T64 SCL SDA SQW(1) F32K(2)
VSS
AI09108
1. Open drain. 2. Defaults to 32 KHz on power-up.
Figure 4.
M41T65 logic diagram
VCC
XI XO M41T65 SCL SDA WDO
(1)
IRQ/FT/OUT(1)
VSS
AI09109
1. Open drain.
Figure 5.
M41T62 connections
NC NC VCC 14 NC 13 12 11 10 9 5 VSS 6 NC 7 NC 8 NC NC IRQ/OUT(2) SCL SDA
16 XI XO VSS SQW
(1)
15
1 2 3 4
QFN
AI09100
1. SQW output defaults to 32 KHz upon power-up. 2. Open drain.
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Description Figure 6. M41T63 connections
VCC NC NC NC
M41T62/63/64/65
16 XI XO VSS SQW(1) 1 2 3 4 5 VSS
15
14
13 12 11 10 9 NC WDO SCL SDA
(2)
6 NC
7 NC
8 NC
AI09190
1. SQW output defaults to 32 KHz upon power-up. 2. Open drain.
Figure 7.
M41T64 connections
VCC 14 NC NC NC 13 12 11 10 9 5 VSS 6 NC 7 NC 8 NC
AI09101
16 XI XO VSS F32K(1) 1 2 3 4
15
NC SQW(2) SCL SDA
1. Enabled on power-up. 2. Open drain.
Figure 8.
M41T65 connections
VCC 14 NC NC NC 13 12 11 10 9 5 VSS 6 NC 7 NC 8 NC
AI09102
16 XI XO VSS WDO
(1)
15
1 2 3 4
NC IRQ/FT/OUT SCL SDA
(1)
1. Open drain.
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M41T62/63/64/65 Table 2.
XI XO SDA SCL IRQ/OUT IRQ/FT/OUT SQW F32K WDO VCC VSS
Description Signal names
Oscillator input Oscillator output Serial data input/output Serial clock input Interrupt or OUT output (open drain) Interrupt, frequency test, or OUT output (open drain) Programmable square wave - defaults to 32 KHz on power-up (open drain for M41T64 only) Dedicated 32 KHz output (M41T64 only) Watchdog timer output (open drain) Supply voltage Ground
Figure 9.
M41T62 block diagram
REAL TIME CLOCK CALENDAR 32KHz OSCILLATOR OSCILLATOR FAIL OFIE DETECT RTC W/ALARM AFE IRQ/OUT(1)
XTAL
SDA
I2C INTERFACE
WATCHDOG SQUARE WAVE SQWE SQW
(2)
SCL
AI08899a
1. Open drain. 2. Defaults to 32 KHz on power-up.
Figure 10. M41T63 block diagram
REAL TIME CLOCK CALENDAR 32KHz OSCILLATOR OSCILLATOR FAIL DETECT RTC W/ALARM SDA WATCHDOG SQUARE WAVE SQWE WDO(1) SQW(2)
AI09191
XTAL
I2C INTERFACE
SCL
1. Open drain. 2. Defaults to 32 KHz on power-up.
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Description Figure 11. M41T64 block diagram
32KE REAL TIME CLOCK CALENDAR 32KHz OSCILLATOR OSCILLATOR FAIL DETECT RTC W/ALARM SDA WATCHDOG SQUARE WAVE SQWE
M41T62/63/64/65
F32K
(1)
XTAL
I2C INTERFACE
SCL
SQW(2)
AI09192
1. Defaults enabled on power-up. 2. Open drain.
Figure 12. M41T65 block diagram
REAL TIME CLOCK CALENDAR 32KHz OSCILLATOR OSCILLATOR FAIL OFIE DETECT FT RTC W/ALARM SDA AFE IRQ/FT/OUT(1)
XTAL
I2C INTERFACE
WATCHDOG
WDO
(1)
SCL
AI09193
1. Open drain.
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M41T62/63/64/65 Figure 13. Hardware hookup for SuperCapTM backup operation
VCC
Description
(1) M41T6x VCC XI XO (2) IRQ/FT/OUT (3) WDO (4) SQW SCL VSS SDA F32K VCC Port Reset Input SQWIN Serial Clock Line Serial Data Line 32KHz CLKIN
AI10400b
MCU
1. Diode required on open drain pin (M41T65 only) for SuperCap (or battery) backup. Low threshold BAT42 diode recommended. 2. For M41T62 and M41T65 (open drain). 3. For M41T63 and M41T65 (open drain). 4. For M41T64 (open drain).
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Operation
M41T62/63/64/65
2
Operation
The M41T6x clock operates as a slave device on the serial bus. Access is obtained by implementing a start condition followed by the correct slave address (D0h). The 16 bytes contained in the device can then be accessed sequentially in the following order:

1st byte: tenths/hundredths of a second register 2nd byte: seconds register 3rd byte: minutes register 4th byte: hours register 5th byte: square wave/day register 6th byte: date register 7th byte: century/month register 8th byte: year register 9th byte: calibration register 10th byte: watchdog register 11th - 15th bytes: alarm registers 16th byte: flags register
2.1
2-wire bus characteristics
The bus is intended for communication between different ICs. It consists of two lines: a bidirectional data signal (SDA) and a clock signal (SCL). Both the SDA and SCL lines must be connected to a positive supply voltage via a pull-up resistor. The following protocol has been defined:

Data transfer may be initiated only when the bus is not busy. During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line, while the clock line is high, will be interpreted as control signals.
Accordingly, the following bus conditions have been defined:
2.1.1
Bus not busy
Both data and clock lines remain high.
2.1.2
Start data transfer
A change in the state of the data line, from high to low, while the clock is high, defines the START condition.
2.1.3
Stop data transfer
A change in the state of the data line, from low to high, while the clock is high, defines the STOP condition.
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Operation
2.1.4
Data valid
The state of the data line represents valid data when after a start condition, the data line is stable for the duration of the high period of the clock signal. The data on the line may be changed during the Low period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a start condition and terminated with a stop condition. The number of data bytes transferred between the start and stop conditions is not limited. The information is transmitted byte-wide and each receiver acknowledges with a ninth bit. By definition a device that gives out a message is called "transmitter," the receiving device that gets the message is called "receiver." The device that controls the message is called "master." The devices that are controlled by the master are called "slaves."
2.1.5
Acknowledge
Each byte of eight bits is followed by one acknowledge bit. This acknowledge bit is a low level put on the bus by the receiver whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed is obliged to generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is a stable Low during the high period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. A master receiver must signal an end of data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this case the transmitter must leave the data line high to enable the master to generate the STOP condition. Figure 14. Serial bus data transfer sequence
DATA LINE STABLE DATA VALID
CLOCK
DATA
START CONDITION
CHANGE OF DATA ALLOWED
STOP CONDITION
AI00587
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Operation Figure 15. Acknowledgement sequence
START SCL FROM MASTER 1 2 8
M41T62/63/64/65
CLOCK PULSE FOR ACKNOWLEDGEMENT 9
DATA OUTPUT BY TRANSMITTER
MSB
LSB
DATA OUTPUT BY RECEIVER
AI00601
2.2
READ mode
In this mode the master reads the M41T6x slave after setting the slave address (see Figure 17 on page 15). Following the WRITE mode control bit (R/W=0) and the acknowledge bit, the word address 'An' is written to the on-chip address pointer. Next the START condition and slave address are repeated followed by the READ mode control bit (R/W=1). At this point the master transmitter becomes the master receiver. The data byte which was addressed will be transmitted and the master receiver will send an acknowledge bit to the slave transmitter. the address pointer is only incremented on reception of an acknowledge clock. The M41T6x slave transmitter will now place the data byte at address An+1 on the bus, the master receiver reads and acknowledges the new byte and the address pointer is incremented to "An+2." This cycle of reading consecutive addresses will continue until the master receiver sends a STOP condition to the slave transmitter. The system-to-user transfer of clock data will be halted whenever the address being read is a clock address (00h to 07h). The update will resume due to a stop condition or when the pointer increments to any non-clock address (08h-0Fh).
Note:
This is true both in READ mode and WRITE mode. An alternate READ mode may also be implemented whereby the master reads the M41T6x slave without first writing to the (volatile) address pointer. The first address that is read is the last one stored in the pointer (see Figure 18 on page 15). Figure 16. Slave address location
R/W
START
SLAVE ADDRESS
A
MSB
1
1
0
1
0
0
LSB 0
AI00602
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M41T62/63/64/65 Figure 17. READ mode sequence
START START R/W BUS ACTIVITY: MASTER R/W
Operation
SDA LINE
S
WORD ADDRESS (An) ACK
S
DATA n
DATA n+1
ACK
ACK
ACK
BUS ACTIVITY: SLAVE ADDRESS
SLAVE ADDRESS STOP
DATA n+X
P
NO ACK
ACK
AI00899
Figure 18. Alternative READ mode sequence
START BUS ACTIVITY: MASTER SDA LINE R/W STOP DATA n ACK ACK DATA n+1 ACK ACK DATA n+X P NO ACK
S
BUS ACTIVITY: SLAVE ADDRESS
AI00895
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Operation
M41T62/63/64/65
2.3
WRITE mode
In this mode the master transmitter transmits to the M41T6x slave receiver. Bus protocol is shown in Figure 19 on page 16. Following the START condition and slave address, a logic '0' (R/W=0) is placed on the bus and indicates to the addressed device that word address "An" will follow and is to be written to the on-chip address pointer. The data word to be written to the memory is strobed in next and the internal address pointer is incremented to the next address location on the reception of an acknowledge clock. The M41T6x slave receiver will send an acknowledge clock to the master transmitter after it has received the slave address see Figure 16 on page 14 and again after it has received the word address and each data byte.
Figure 19. WRITE mode sequence
START STOP WORD ADDRESS (An) ACK ACK DATA n DATA n+1 DATA n+X P ACK ACK ACK
AI00591
BUS ACTIVITY: MASTER
SDA LINE
S
BUS ACTIVITY: SLAVE ADDRESS
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R/W
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M41T62/63/64/65
Clock operation
3
Clock operation
The M41T6x is driven by a quartz-controlled oscillator with a nominal frequency of 32.768 kHz. The accuracy of the real-time clock depends on the frequency of the quartz crystal that is used as the time-base for the RTC. The eight byte clock register (see Table 3: M41T62 register map, Table 4: M41T63 register map, Table 5: M41T64 register map, and Table 6: M41T65 register map) is used to both set the clock and to read the date and time from the clock, in a binary coded decimal format. Tenths/hundredths of seconds, seconds, minutes, and hours are contained within the first four registers. A WRITE to any clock register will result in the tenths/hundredths of seconds being reset to "00," and tenths/hundredths of seconds cannot be written to any value other than "00." Bits D0 through D2 of register 04h contain the day (day of week). Registers 05h, 06h, and 07h contain the date (day of month), month, and years. The ninth clock register is the calibration register (this is described in the clock calibration section). Bit D7 of register 01h contains the STOP bit (ST). Setting this bit to a '1' will cause the oscillator to stop. When reset to a '0' the oscillator restarts within one second (typical). Upon initial power-up, the user should set the ST bit to a '1,' then immediately reset the ST bit to '0.' This provides an additional "kick-start" to the oscillator circuit. Bit D7 of register 02h (minute register) contains the oscillator fail interrupt enable bit (OFIE). When the user sets this bit to '1,' any condition which sets the oscillator fail bit (OF) (see Oscillator stop detection on page 29) will also generate an interrupt output. Bits D6 and D7 of clock register 06h (century/month register) contain the CENTURY bit 0 (CB0) and CENTURY bit 1 (CB1). A WRITE to ANY location within the first eight bytes of the clock register (00h-07h), including the OFIE bit, RS0-RS3 bit, and CB0-CB1 bits will result in an update of the system clock and a reset of the divider chain. This could result in an inadvertent change of the current time. These non-clock related bits should be written prior to setting the clock, and remain unchanged until such time as a new clock time is also written. The eight clock registers may be read one byte at a time, or in a sequential block. Provision has been made to assure that a clock update does not occur while any of the eight clock addresses are being read. If a clock address is being read, an update of the clock registers will be halted. This will prevent a transition of data during the READ.
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Clock operation
M41T62/63/64/65
3.1
RTC registers
The M41T6x user interface is comprised of 16 memory mapped registers which include clock, calibration, alarm, watchdog, flags, and square wave control. The eight clock counters are accessed indirectly via a set of buffer/transfer registers while the other eight registers are directly accessed. Data in the clock and alarm registers is in BCD format.
Figure 20. Buffer/transfer registers
CLOCK COUNTERS ARE ACCESSED INDIRECTLY THRU BUFFER/TRANSFER REGISTERS
AT START OF READ, UDATES FROM COUNTERS ARE HALTED AND PRESENT TIME IS FROZEN IN BUFFER/TRANSFER REGISTERS.
32KHz OSC DIVIDE BY 32768
READ / WRITE BUFFER TRANSFER REGISTERS
1 Hz
COUNTER COUNTER
I2C
2
I2C INTERFACE
SECONDS MINUTES HOURS DAY-OF-WEEK DATE MONTHS YEARS CENTURIES
COUNTER COUNTER COUNTER COUNTER COUNTER
COUNTER
DATA TRANSFERRED OUT OF I2C INTERFACE ON 8th FALLING EDGE OF SCL (ON WRITES)
NON-CLOCK REGISTERS
CALIBRATION WATCHDOG FLAGS
NON-CLOCK REGISTERS ARE DIRECTLY ACCESSED
ON WRITES, DATA TRANSFERRED FROM BUFFERS TO COUNTERS WHEN ADDRESS POINTER INCREMENTS TO 8 OR WHEN I2C STOP CONDITION IS RECEIVED
AM04890v1
Updates
During normal operation when the user is not accessing the device, the buffer/transfer registers are kept updated with a copy of the RTC counters. At the start of an I2C read or write cycle, the updating is halted and the present time is frozen in the buffer/transfer registers.
Reads of the clock registers
By halting the updates at the start of an I2C access, the user is ensured that all the data transferred out during a read sequence comes from the same instant in time.
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M41T62/63/64/65
Clock operation
Write timing
When writing to the device, the data is shifted into the M41T62's I2C interface on the rising edge of the SCL signal. As shown in Figure 20, on the 8th clock cycle, the data is transferred from the I2C block into whichever register is being pointed to by the address pointer (not shown).
Writes to the clock registers (addresses 0-7)
Data written to the clock registers (addresses 0-7) is held in the buffer registers until the address pointer increments to 8, or an I2C stop condition occurs, at which time the data in the buffer/registers is simultaneously copied into the counters, and then the clock is restarted.
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Clock operation Table 3.
Addr D7 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh OUT RB2 AFE RPT4 RPT3 RPT2 RPT1 WDF ST OFIE 0 RS3 0 CB1 0 RS2 0 CB0 0 D6 D5 D4 D3 D2 D1 D0
M41T62/63/64/65 M41T62 register map
Function/range BCD format 10ths/100ths of seconds Seconds Minutes Hours Day Date Century/ month Year Calibration RB1 RB0 Watchdog Al month Al date Al hour Al min Al sec 0 Flags 01-12 01-31 00-23 00-59 00-59 00-99 00-59 00-59 00-23 01-7 01-31 0-3/01-12 00-99
0.1 seconds 10 seconds 10 minutes 10 hours RS1 RS0
0.01 seconds Seconds Minutes Hours (24-hour format) 0 Day of week Date: day of month Month Year Calibration BMB2 Al 10M BMB1 BMB0
10 date 10M
10 years 0 BMB4 SQWE RPT5 0 S BMB3 0
Alarm month Alarm date Alarm hour Alarm minutes Alarm seconds 0 OF 0
AI 10 date AI 10 hour
Alarm 10 minutes Alarm 10 seconds AF 0 0
Keys: 0 = must be set to '0' AF = alarm flag (read only) AFE = alarm flag enable flag BMB0 - BMB4 = watchdog multiplier bits CB0-CB1 = century bits OF = oscillator fail bit OFIE = oscillator fail interrupt enable bit OUT = output level RB0 - RB2 = watchdog resolution bits RPT1-RPT5 = alarm repeat mode bits RS0-RS3 = SQW frequency bits S = sign bit SQWE = square wave enable bit ST = stop bit WDF = watchdog flag bit (read only)
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M41T62/63/64/65 Table 4.
Addr D7 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 0 RB2 0 RPT4 RPT3 RPT2 RPT1 WDF ST 0 0 RS3 0 CB1 0 RS2 0 CB0 0 D6 D5 D4 D3 D2 D1 D0
Clock operation M41T63 register map
Function/range BCD format 10ths/100ths of seconds Seconds Minutes Hours Day Date Century/ month Year Calibration RB1 RB0 Watchdog Al Month Al date Al hour Al min Al sec 0 Flags 01-12 01-31 00-23 00-59 00-59 00-99 00-59 00-59 00-23 01-7 01-31 0-3/01-12 00-99
0.1 seconds 10 seconds 10 minutes 10 hours RS1 RS0 0
0.01 seconds Seconds Minutes Hours (24-hour format) Day of week Date: day of month Month Year Calibration BMB2 Al 10M BMB1 BMB0
10 date 10M
10 years 0 S
BMB4 BMB3 SQWE RPT5 0 0
Alarm month Alarm date Alarm hour Alarm minutes Alarm seconds 0 OF 0
AI 10 date AI 10 hour
Alarm 10 minutes Alarm 10 seconds AF 0 0
Keys: 0 = must be set to '0' AF = alarm flag (read only) BMB0 - BMB4 = watchdog multiplier bits CB0-CB1 = century bits OF = oscillator fail bit RB0 - RB2 = watchdog resolution bits RPT1-RPT5 = alarm repeat mode bits RS0-RS3 = SQW frequency bits S = sign bit SQWE = square wave enable bit ST = stop bit WDF = watchdog flag bit (read only)
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Clock operation Table 5.
Addr D7 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 0 RB2 0 RPT4 RPT3 RPT2 RPT1 WDF ST 0 0 RS3 0 CB1 0 RS2 0 CB0 D6 D5 D4 D3 D2 D1 D0
M41T62/63/64/65 M41T64 register map
Function/range BCD format 10ths/100ths of seconds Seconds Minutes Hours Day Date Century/ month Year Calibration RB1 RB0 Watchdog Al month Al date Al hour Al min Al sec 0 Flags 01-12 01-31 00-23 00-59 00-59 00-99 00-59 00-59 00-23 01-7 01-31 0-3/01-12 00-99
0.1 seconds 10 seconds 10 minutes 10 hours RS1 RS0
0.01 seconds Seconds Minutes Hours (24-hour format) 0 Day of week Date: day of month Month Year Calibration BMB2 BMB1 BMB0
10 Date 0 10M
10 years 0 BMB4 SQWE RPT5 0 S BMB3
32KE Al 10M AI 10 date AI 10 hour
Alarm month Alarm date Alarm hour Alarm minutes Alarm seconds 0 OF 0
Alarm 10 minutes Alarm 10 seconds AF 0 0
Keys: 0 = must be set to '0' 32KE = 32 KHz enable bit AF = alarm flag (read only) BMB0 - BMB4 = watchdog multiplier bits CB0-CB1 = century bits OF = oscillator fail bit RB0 - RB2 = watchdog resolution bits RPT1-RPT5 = alarm repeat mode bits RS0-RS3 = SQW frequency bits S = sign bit SQWE = square wave enable bit ST = stop bit WDF = watchdog flag bit (read only)
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M41T62/63/64/65 Table 6.
Addr D7 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh OUT RB2 AFE RPT4 RPT3 RPT2 RPT1 WDF ST OFIE 0 0 0 CB1 0 0 0 CB0 0 0 D6 D5 D4 D3 D2 D1 D0
Clock operation M41T65 register map
Function/range BCD format 10ths/100ths of seconds Seconds Minutes Hours Day Date Century/ month Year Calibration RB1 RB0 Watchdog Al month Al date Al hour Al min Al sec 0 Flags 01-12 01-31 00-23 00-59 00-59 00-99 00-59 00-59 00-23 01-7 01-31 0-3/01-12 00-99
0.1 seconds 10 seconds 10 minutes 10 hours 0 10 date 10M
0.01 seconds Seconds Minutes Hours (24-hour format) 0 Day of week Date: day of month Month Year Calibration BMB2 Al 10M BMB1 BMB0
10 years FT BMB4 0 RPT5 0 S BMB3 0
Alarm month Alarm date Alarm hour Alarm minutes Alarm seconds 0 OF 0
AI 10 date AI 10 hour
Alarm 10 minutes Alarm 10 seconds AF 0 0
Keys: 0 = must be set to '0' AF = alarm flag (read only) AFE = alarm flag enable flag BMB0 - BMB4 = watchdog multiplier bits CB0-CB1 = century bits FT = frequency test bit OF = oscillator fail bit OFIE = oscillator fail interrupt enable bit OUT = output level RB0 - RB2 = watchdog resolution bits RPT1-RPT5 = alarm repeat mode bits S = sign bit ST = stop bit WDF = watchdog flag bit (read only)
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Clock operation
M41T62/63/64/65
3.2
Calibrating the clock
The M41T6x real-time clock is driven by a quartz controlled oscillator with a nominal frequency of 32,768 Hz. This provides the time-base for the RTC. The accuracy of the clock depends on the frequency accuracy of the crystal, and the match between the capacitive load of the oscillator circuit and the capacitive load for which the crystal was trimmed. The M41T6x oscillator is designed for use with a 6 - 7 pF crystal load capacitance. When the calibration circuit is properly employed, accuracy improves to better than 2 ppm at 25 C. The oscillation rate of crystals changes with temperature (see Figure 21 on page 25). Therefore, the M41T6x design employs periodic counter correction. The calibration circuit adds or subtracts counts from the oscillator divider circuit at the divide by 256 stage, as shown in Figure 22 on page 25. The number of times pulses which are blanked (subtracted, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five calibration bits found in the calibration register. Adding counts speeds the clock up, subtracting counts slows the clock down. The calibration bits occupy the five lower order bits (D4-D0) in the calibration register (08h). These bits can be set to represent any value between 0 and 31 in binary form. Bit D5 is a sign bit; '1' indicates positive calibration, '0' indicates negative calibration. Calibration occurs within a 64 minute cycle. The first 62 minutes in the cycle may, once per minute, have one second either shortened by 128 or lengthened by 256 oscillator cycles. If a binary '1' is loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on. Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125,829,120 actual oscillator cycles, that is +4.068 or -2.034 ppm of adjustment per calibration step in the calibration register. Assuming that the oscillator is running at exactly 32,768 Hz, each of the 31 increments in the calibration byte would represent +10.7 or -5.35 seconds per day which corresponds to a total range of +5.5 or -2.75 minutes per month (see Figure 22 on page 25). Two methods are available for ascertaining how much calibration a given M41T6x may require:
The first involves setting the clock, letting it run for a month and comparing it to a known accurate reference and recording deviation over a fixed period of time. Calibration values, including the number of seconds lost or gained in a given period, can be found in application note AN934, "TIMEKEEPER(R) calibration." This allows the designer to give the end user the ability to calibrate the clock as the environment requires, even if the final product is packaged in a non-user serviceable enclosure. The designer could provide a simple utility that accesses the calibration byte. The second approach is better suited to a manufacturing environment, and involves the use of either the SQW pin (M41T62/63/64) or the IRQ/FT/OUT pin (M41T65). The SQW pin will toggle at 512 Hz when RS3 = '0,' RS2 = '1,' RS1 = '1,' RS0 = '0,' SQ WE = '1,' and ST = '0.' Alternatively, for the M41T65, the IRQ/FT/OUT pin will toggle at 512 Hz when FT and OUT bits = '1' and ST = '0.'
Any deviation from 512 Hz indicates the degree and direction of oscillator frequency shift at the test temperature. For example, a reading of 512.010124 Hz would indicate a +20 ppm oscillator frequency error, requiring a -10 (XX001010) to be loaded into the calibration byte for correction. Note that setting or changing the calibration byte does not affect the frequency test or square wave output frequency.
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M41T62/63/64/65 Figure 21. Crystal accuracy across temperature
Frequency (ppm) 20 0 -20 -40 -60 -80 -100 -120 -140 -160 -40 -30 -20 -10 0 10 20 30 40 50 60 F = K x (T - T )2 O F
2 2 K = -0.036 ppm/C 0.006 ppm/C
Clock operation
TO = 25C 5C
70
80
AI07888
Temperature C
Figure 22. Calibration waveform
NORMAL
POSITIVE CALIBRATION
NEGATIVE CALIBRATION
AI00594b
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Clock operation
M41T62/63/64/65
3.3
Setting alarm clock registers
Address locations 0Ah-0Eh contain the alarm settings. The alarm can be configured to go off at a prescribed time on a specific month, date, hour, minute, or second, or repeat every year, month, day, hour, minute, or second. Bits RPT5-RPT1 put the alarm in the repeat mode of operation. Table 7 on page 26 shows the possible configurations. Codes not listed in the table default to the once per second mode to quickly alert the user of an incorrect alarm setting. When the clock information matches the alarm clock settings based on the match criteria defined by RPT5-RPT1, the AF (alarm flag) is set. If AFE (alarm flag enable) is also set (M41T62/65), the alarm condition activates the IRQ/OUT or IRQ/FT/OUT pin. To disable the alarm, write '0' to the alarm date register and to RPT5-RPT1.
Note:
If the address pointer is allowed to increment to the flag register address, an alarm condition will not cause the interrupt/flag to occur until the address pointer is moved to a different address. It should also be noted that if the last address written is the "Alarm Seconds," the address pointer will increment to the flag address, causing this situation to occur. The IRQ output is cleared by a READ to the flags register as shown in Figure 23 on page 26. A subsequent READ of the flags register is necessary to see that the value of the alarm flag has been reset to '0.' Figure 23. Alarm interrupt reset waveform
Register address 0Eh 0Fh 00h
ALARM FLAG BIT (AF)
IRQ/OUT or IRQ/FT/OUT
HIGH-Z
AI08898
Table 7.
RPT5 1 1 1 1 1 0
Alarm repeat modes
RPT4 1 1 1 1 0 0 RPT3 1 1 1 0 0 0 RPT2 1 1 0 0 0 0 RPT1 1 0 0 0 0 0 Alarm setting Once per second Once per minute Once per hour Once per day Once per month Once per year
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Clock operation
3.4
Watchdog timer
The watchdog timer can be used to detect an out-of-control microprocessor. The user programs the watchdog timer by setting the desired amount of time-out into the watchdog register, address 09h. Bits BMB4-BMB0 store a binary multiplier and the three bits RB2-RB0 select the resolution where: 000=1/16 second (16 Hz); 001=1/4 second (4 Hz); 010=1 second (1 Hz); 011=4 seconds (1/4 Hz); and 100 = 1 minute (1/60 Hz).
Note:
Invalid combinations (101, 110, and 111) will NOT enable a watchdog time-out. Setting BMB4-BMB0 = 00000 with any combination of RB2-RB0, other than 000, will result in an immediate watchdog time-out. The amount of time-out is then determined to be the multiplication of the five-bit multiplier value with the resolution. (For example: writing 00001110 in the watchdog register = 3*1 or 3 seconds). If the processor does not reset the timer within the specified period, the M41T6x sets the WDF (watchdog flag) and generates an interrupt on the IRQ pin (M41T62), or a watchdog output pulse (M41T63 and M41T65 only) on the WDO pin. The watchdog timer can only be reset by having the microprocessor perform a WRITE of the watchdog register. The time-out period then starts over. Should the watchdog timer time-out, any value may be written to the watchdog register in order to clear the IRQ pin. A value of 00h will disable the watchdog function until it is again programmed to a new value. A READ of the flags register will reset the watchdog flag (bit D7; register 0Fh). The watchdog function is automatically disabled upon power-up, and the watchdog register is cleared.
Note:
A WRITE to any clock register will restart the watchdog timer.
3.5
Watchdog output (WDO - M41T63/65 only)
If the processor does not reset the watchdog timer within the specified period, the watchdog output (WDO) will pulse low for trec (see Table 18 on page 35). This output may be connected to the reset input of the processor in order to generate a processor reset. After a watchdog time-out occurs, the timer will remain disabled until such time as a new countdown value is written into the watchdog register.
Note:
The crystal oscillator must be running for the WDO pulse to be available. The WDO output is an N-channel, open drain output driver (with IOL as specified in Table 14 on page 33).
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Clock operation
M41T62/63/64/65
3.6
Square wave output (M41T62/63/64)
The M41T62/63/64 offers the user a programmable square wave function which is output on the SQW pin. RS3-RS0 bits located in 04h establish the square wave output frequency. These frequencies are listed in Table 8. Once the selection of the SQW frequency has been completed, the SQW pin can be turned on and off under software control with the square wave enable bit (SQWE) located in register 0Ah. The SQW output is an N-channel, open drain output driver for the M41T64, and a full CMOS output driver for the M41T62/63. The initial power-up default for the SQW output is 32 KHz (except for M41T64, which defaults disabled). Table 8. Square wave output frequency
Square wave bits RS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 RS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 RS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 RS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Square wave Frequency None 32.768 8.192 4.096 2.048 1.024 512 256 128 64 32 16 8 4 2 1 Units - kHz kHz kHz kHz kHz Hz Hz Hz Hz Hz Hz Hz Hz Hz Hz
3.7
Full-time 32 KHz square wave output (M41T64)
The M41T64 offers the user a special 32 KHz square wave function which is enabled on power-up to output on the F32K pin as long as VCC 1.3 V, and the oscillator is running (ST bit = '0'). This function is available within one second (typ) of initial power-up and can only be disabled by setting the 32KE bit to '0' or the ST bit to '1.' If not used, the F32K pin should be disconnected and allowed to float.
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Clock operation
3.8
Century bits
These two bits will increment in a binary fashion at the turn of the century, and handle all leap years correctly. See Table 10 on page 30 for additional explanation.
3.9
Output driver pin (M41T62/65)
When the OFIE bit, AFE bit, and watchdog register are not set to generate an interrupt, the IRQ/OUT pin becomes an output driver that reflects the contents of D7 of the calibration register. In other words, when D7 (OUT Bit) is a '0,' then the IRQ/OUT pin will be driven low.
Note:
The IRQ/OUT pin is an open drain which requires an external pull-up resistor.
3.10
Oscillator stop detection
If the oscillator fail (OF) bit is internally set to a '1,' this indicates that the oscillator has either stopped, or was stopped for some period of time and can be used to judge the validity of the clock and date data. This bit will be set to '1' any time the oscillator stops. In the event the OF bit is found to be set to '1' at any time other than the initial power-up, the STOP bit (ST) should be written to a '1,' then immediately reset to '0.' This will restart the oscillator. The following conditions can cause the OF bit to be set:
The first time power is applied (defaults to a '1' on power-up).
Note:
If the OF bit cannot be written to '0' four (4) seconds after the initial power-up, the STOP bit (ST) should be written to a '1,' then immediately reset to '0.'

The voltage present on VCC or battery is insufficient to support oscillation. The ST bit is set to '1.' External interference of the crystal
If the oscillator fail interrupt enable bit (OFIE) is set to a '1,' the IRQ pin will also be activated. The IRQ output is cleared by resetting the OFIE or OF bit to '0' (NOT by reading the flag register). The OF bit will remain set to '1' until written to logic '0.' The oscillator must start and have run for at least 4 seconds before attempting to reset the OF bit to '0.' If the trigger event occurs during a power-down condition, this bit will be set correctly.
3.11
Initial power-on defaults
Upon application of power to the device, the register bits will initially power-on in the state indicated in Table 9.
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Clock operation Table 9.
Condition
M41T62/63/64/65 Initial power-on default values
Device M41T62 ST OF OFIE OUT FT AFE SQWE 32KE RS3-1 RS0 Watchdog 0 0 0 0 1 1 1 1 0 N/A N/A 0 1 N/A 0 1 1 0 N/A N/A N/A 1 N/A 0 0 0 N/A 1 1 1 N/A 0 0 0 0
Initial power-up(1)
M41T63 M41T64 M41T65
N/A N/A N/A N/A N/A N/A 1 0 0
1. All other control bits power up in an undetermined state.
Table 10.
Century bits examples
CB1 0 1 0 1 Leap year? Yes No No No Example(1) 2000 2100 2200 2300
CB0 0 0 1 1
1. Leap year occurs every four years (for years evenly divisible by four), except for years evenly divisible by 100. The only exceptions are those years evenly divisible by 400 (the year 2000 was a leap year, year 2100 is not).
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Maximum ratings
4
Maximum ratings
Stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 11.
Sym TSTG VCC TSLD(3) VIO IO PD VESD(HBM) VESD(RCDM)
Absolute maximum ratings
Parameter Storage temperature (VCC off, oscillator off) Supply voltage Lead solder temperature for 10 seconds Input or output voltages Output current Power dissipation Electro-static discharge voltage (human body model) Electro-static discharge voltage (robotic charged device model) TA = 25 C TA = 25 C Conditions(1) Value(2) -55 to 125 -0.3 to 5.0 260 -0.2 to Vcc+0.3 20 1 >1500 >1000 Unit
C
V C V mA W V V
1. Test conforms to JEDEC standard. 2. Data based on characterization results, not tested in production. 3. Reflow at peak temperature of 260 C. The time above 255 C must not exceed 30 seconds.
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DC and AC parameters
M41T62/63/64/65
5
DC and AC parameters
This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC Characteristic tables are derived from tests performed under the measurement conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters. Table 12. Operating and AC measurement conditions(1)
Parameter Supply voltage (VCC) Ambient operating temperature (TA) Load capacitance (CL) Input rise and fall times Input pulse voltages Input and output timing ref. voltages
1. Output Hi-Z is defined as the point where data is no longer driven.
M41T6x 1.3 V to 4.4 V -40 to 85 C 50 pF 5 ns 0.2 VCC to 0.8 VCC 0.3 VCC to 0.7 VCC
Figure 24. AC measurement I/O waveform
0.8VCC 0.7VCC 0.3VCC
AI02568
0.2VCC
Figure 25. Crystal isolation example
Local Grounding Plane (Layer 2)
XI
Crystal
XO GND
AI09127
Note:
Substrate pad should be tied to VSS.
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M41T62/63/64/65 Table 13.
Symbol CIN COUT(3) tLP Input capacitance Output capacitance Low-pass filter input time constant (SDA and SCL)
DC and AC parameters Capacitance
Parameter(1)(2) Min Max 7 10 50 Unit pF pF ns
1. Effective capacitance measured with power supply at 3.6 V; sampled only, not 100% tested. 2. At 25C, f = 1 MHz. 3. Outputs deselected.
Table 14.
Sym
VCC(2)
DC characteristics
Parameter Test condition(1) Clock Min 1.0 1.3 4.4 V 3.6 V 50 35 30 20 950 375 350 310 -0.2 0.7 VCC VCC = 4.4 V, IOL = 3.0 mA (CMOS or open drain) 0.3 VCC VCC+0.3 0.4 0.4 2.4 4.4 1 1 700 SCL = 400 kHz (no load) Typ Max 4.4 4.4 100 70 Unit V V A A A A A nA nA nA nA V V V V V V A A
Operating voltage
I2C
bus (400 kHz)
ICC1 Supply current
3.0 V 2.5 V 2.0 V
ICC2
Supply current (standby)
4.4 V SCL = 0 Hz 3.6 V all inputs SQW off VCC - 0.2 V 3.0 V at 25 C VSS + 0.2 V 2.0 V at 25 C
VIL VIH
Input low voltage Input high voltage
VOL
Output low voltage VCC = 4.4 V, IOL = 1.0 mA (SQW, WDO, IRQ)
VOH Output high voltage Pull-up supply voltage (open drain) ILI ILO Input leakage current Output leakage current
VCC = 4.4 V, IOH = -1.0 mA (push-pull) IRQ/OUT, IRQ/FT/OUT, WDO, SQW (M41T64 only) 0 V VIN VCC 0 V VOUT VCC
1. Valid for ambient operating temperature: TA = -40 to 85 C; VCC = 1.3 V to 4.4 V (except where noted). 2. Oscillator startup guaranteed at 1.5 V only.
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DC and AC parameters Table 15.
Sym fO RS CL Resonant frequency Series resistance (TA = -40 to 70 C, oscillator startup at 2.0 V) Load capacitance
M41T62/63/64/65
Crystal electrical characteristics
Parameter(1)(2) Min 6 Typ 32.768 75
(3)(4)
Max
Units kHz k pF
1. For the QFN16 package, user-supplied external crystals are required. The 6 and 7 pF crystals listed in Table 16 below have been evaluated by ST and have been found to be satisfactory for use with the M41T6x series RTC. 2. Load capacitors are integrated within the M41T6x. Circuit board layout considerations for the 32.768 kHz crystal of minimum trace lengths and isolation from RF generating signals should be taken into account. 3. Guaranteed by design. 4. RS (max) = 65 k for TA = -40 to 85 C and oscillator startup at 1.5 V.
Table 16.
Crystals suitable for use with M41T6x series RTCs
Manufacturer's specifications
Vendor
Order number
Package
ESR max 50 k
Rated Rated Temp. tolerance load range (C) at 25 C cap. -40/+85 -40/+85 -10/+60 -40/+85 -10/+60 -40/+85 -40/+85 -40/+85 -20/+60 -20/+60 -40/+85 -40/+85 -40/+85 -40/+85 -40/+85 -10/+60 20 ppm 20 ppm 20 ppm 20 ppm 20 ppm 20 ppm 20 ppm 20 ppm 20 ppm 20 ppm 20 ppm 20 ppm 20 ppm 20 ppm 20 ppm 20 ppm 6 pF 7 pF 6 pF 7 pF 6 pF 7 pF 7 pF 7 pF 6 pF 6 pF 6 pF 7 pF 7 pF 6 pF 7 pF 6 pF
Citizen Citizen Ecliptek Ecliptek ECS ECS ECS Epson Fox Fox Fox Fox Micro Crystal
CMJ206T-32.768KDZB-UB CM315-32.768KDZY-UB E4WCDA06-32.768K E5WSDC 07 - 32.768K ECS-.327-6-17X-TR ECS-.327-7-34B-TR ECS-.327-7-38-TR MC-146 32.7680KA-AG: ROHS(1) 298LF-0.032768-19 299LF-0.032768-37 414LF-0.032768-12 501LF-0.032768-5 MS3V-T1R 32.768KHZ 7PF 20PPM
8.3 x 2.5 mm leaded SMT
3.2 x 1.5 x 0.9 mm SMT 70 k 2.0 x 6.0 mm thru-hole 7 x 1.5 x 1.4 mm SMT 50 k 65 k
3.8 x 8.5 x 2.5 mm SMT 50 k 3.2 x 1.5 x 0.9 mm SMT 70 k 7 x 1.5 x 1.4 mm SMT 7 x 1.5 x 1.4 mm SMT 1.5 x 5.0 mm thru-hole 2.0 x 6.0 mm thru-hole 65 k 65 k 50 k 50 k
3.8 x 8.5 x 2.5 mm SMT 50 k 7 x 1.5 x 1.4 mm SMT 6.7 x 1.4 mm leaded SMT 65 k 65 k
Pletronics SM20S - 32.768K - 6pF Seiko Seiko SSPT7F-7PF20PPM VT200F-6PF20PPM
3.8 x 8.5 x 2.5 mm SMT 50 k 7 x 1.5 x 1.4 mm SMT 2.0 x 6.0 mm thru-hole 65 k 50 k
1. Epson MC-146 32.7680KA-E: ROHS is 6 pF version.
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M41T62/63/64/65 Table 17.
Symbol
VSTA
DC and AC parameters Oscillator characteristics
Parameter Oscillator start voltage Oscillator start time XIN capacitance XOUT capacitance IC-to-IC frequency variation
(1)
Conditions 10 seconds VCC = 3.0 V
Min 1.5
Typ
Max
Unit V
tSTA Cg Cd
1 12 12 -10 +10
s pF pF ppm
1. Reference value. TA = 25 C, VCC = 3.0 V, CMJ-145 (CL = 6 pF, 32,768 Hz) manufactured by Citizen, CL = Cg * Cd / (Cg + Cd).
Figure 26. Bus timing requirements sequence
SDA tBUF tHD:STA tR SCL tHIGH P S tLOW tSU:DAT tHD:DAT tSU:STA tSU:STO tF tHD:STA
SR
P
AI00589
Table 18.
Sym fSCL tLOW tHIGH tR tF tHD:STA tSU:STA tSU:DAT(2) tHD:DAT tSU:STO tBUF trec
AC characteristics
Parameter(1) SCL clock frequency Clock low period Clock high period SDA and SCL rise time SDA and SCL fall time START condition hold time (after this period the first clock pulse is generated) START condition setup time (only relevant for a repeated start condition) Data setup time Data hold time STOP condition setup time Time the bus must be free before a new transmission can start Watchdog output pulse width 600 600 100 0 600 1.3 96 98 Min 0 1.3 600 300 300 Max 400 Units kHz s ns ns ns ns ns ns s ns s ms
1. Valid for ambient operating temperature: TA = -40 to 85 C; VCC = 1.3 to 4.4 V (except where noted). 2. Transmitter must internally provide a hold time to bridge the undefined region (300 ns max) of the falling edge of SCL.
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Package mechanical information
M41T62/63/64/65
6
Package mechanical information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark.
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Package mechanical information
Figure 27. QFN16 - 16-lead, quad, flat package, no lead, 3 x 3 mm body size, outline
D
E
A3
A1
A
ddd C
b L
e K
1 2
E2
3
Ch
K D2
QFN16-A
Note:
Drawing is not to scale. Table 19. QFN16 - 16-lead, quad, flat package, no lead, 3 x 3 mm body size, mechanical data
mm Symb Typ A A1 A3 b D D2 E E2 e K L ddd Ch N 0.90 0.02 0.20 0.25 3.00 1.70 3.00 1.70 0.50 0.20 0.40 - - Min 0.80 0.00 - 0.18 2.90 1.55 2.90 1.55 - - 0.30 0.08 0.33 16 Max 1.00 0.05 - 0.30 3.10 1.80 3.10 1.80 - - 0.50 - - Typ 0.035 0.001 0.008 0.010 0.118 0.067 0.118 0.067 0.020 0.008 0.016 - - Min 0.032 0.000 - 0.007 0.114 0.061 0.114 0.061 - - 0.012 0.003 0.013 16 Max 0.039 0.002 - 0.012 0.122 0.071 0.122 0.071 - - 0.020 - - inches
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Package mechanical information
M41T62/63/64/65
Figure 28. QFN16 - 16-lead, quad, flat package, no lead, 3 x 3 mm, recommended footprint
1.60
3.55
2.0
0.28
AI09126
Note:
Dimensions shown are in millimeters (mm).
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M41T62/63/64/65
Part numbering
7
Part numbering
Table 20.
Example:
Ordering information scheme
M41T 62 Q 6 F
Device family M41T
Device type and supply voltage 62 = VCC = 1.3 V to 4.4 V 63 = VCC = 1.3 V to 4.4 V 64 = VCC = 1.3 V to 4.4 V 65 = VCC = 1.3 V to 4.4 V Package Q = QFN16 (3 mm x 3 mm)
Temperature range 6 = -40 C to 85 C
Shipping method for SOIC F = ECOPACK(R) package, tape & reel
For other options, or for more information on any aspect of this device, please contact the ST sales office nearest you.
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Revision history
M41T62/63/64/65
8
Revision history
Table 21.
Date 13-Nov-2003 19-Nov-2003 25-Dec-2003 14-Jan-2004
Document revision history
Revision 1.0 1.1 2 2.1 First issue Add features, update characteristics (Figure 1, Figure 3, Figure 4, Figure 9, Figure 23; Table 2, Table 3, Table 9, Table 11, Table 14, Table 18) Reformatted; add crystal isolation, footprint (Figure 25) Update characteristics (Figure 1, Figure 9, Figure 25; Table 1, Table 3. Table 9, Table 14) Update characteristics and mechanical dimensions (Figure 1, Figure 3, Figure 2, Figure 4, Figure 5, Figure 6, Figure 9, Figure 10, Figure 11, Figure 12, Figure 27, Figure 28; Table 3, Table 4, Table 5, Table 6, Table 9, Table 11, Table 14, Table 19) Update characteristics (Figure 7, Figure 8, Figure 11; Table 2, Table 14) Reformat and republish Update characteristics (Figure 5, Figure 6, Figure 7, Figure 8, Figure 25, Figure 28; Table 11, Table 14, Table 15) Correct diagrams; update characteristics (Figure 3, Figure 2, Figure 25; Table 2, Table 14, Table 17) Update characteristics (Table 11, Table 14) Correct footprint dimensions; update characteristics (Figure 3, Figure 7, Figure 11, Figure 13, Figure 28; Table 1, Table 2, Table 5, Table 8, Table 9, Table 11, Table 12, Table 14, Table 15, Table 17, Table 18) Add package comparison and mechanical data (in Feature summary on page 1, Figure 28) Update: bus operating voltage, characteristics, add Lead-free text (Figure 13; Table 11, Table 12, Table 14, Table 18, Table 20) Update ESD:HBM rating, crystal characteristics (Table 11, Table 15) Changed document to new template; small text changes for Feature summary on page 1 Minor textual changes; updated Section 3.2; footnote 3 in Table 11; footnote 1 in Table 15; text in Section 6; Table 16, 18. Updated title of datasheet, Features, Section 1, Section 3.1, 3.2, 3.4, 3.10, Section 4, Figure 23, Table 16; added Figure 20, added embedded crystal package LCC8 (updated Figure 1, 5, 29, Table 20) Removed LCC8 package option throughout document; removed footnote from Table 14. Changes
27-Feb-2004
2.2
02-Mar-2004 26-Apr-2004 13-May-2004 06-Aug-2004 11-Oct-2004
2.3 3 4 5 6
18-Jan-2005
7
05-May-2005 31-Oct-2005 30-Nov-2005 22-Aug-2006 26-Jan-2010
8 9 10 11 12
07-May-2010
13
25-May-2010
14
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